opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

HDL libraries and projects

A small, light weight, RISC CPU soft core

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

CHIP-8 console on FPGA

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

An attempt at a small Verilog implementation of the original Apple 1 on an FPGA

Riscv32 CPU Project

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog